Impact of Packaging Design on Reliability of Large Die Cu/low-κ (BD) Interconnect

This paper presents the study on the effect of low κ stacked layer, chip pad design structures, and shift pad design of a large die size Cu/low κ (BD) chip for improving assembly and reliability performance on organic buildup substrate FCBGA (FlipChip Ball Grid Array). Bump shear characterization has been performed on the integrity of different stacked layer and pad structure, supported by bump shear modeling analysis. Initial reliability testing was performed on assembled package to identify the best choice of design and finally implemented on the reliability test vehicle for verification. In addition, a potential chip crack problem due to excessive warpage in FCBGA with large die assembly is examined and a simple failure criterion is proposed. Introduction With shrinking of CMOS device, Cu/Low κ interconnection has been adopted in the IC process for the RC delay reduction. And it is moving towards finer technology nodes from 90nm to 65 nm and 45nm. The low κ dielectric is critical in ensuing better capacitance, device speed and signal integrity of the Cu interconnect. However, mechanically the dielectric material has lower modulus, brittle and lower adhesion strength [1,2]. Many works have reported concerns on the mechanical integrity of Cu/low κ chip and its susceptibility to chip failure in reliability testing [2,3,4,5]. On the other hand, Flip Chip package is gaining increased popularity as the preferred solution for high performance ASIC and microprocessor devices, with a trend towards more I/O, finer pitch and larger chip size. For cost consideration, organics substrate has been employed instead of the more expensive ceramic substrate [6,7]. The tradeoff is CTE mismatch between the silicon chip and substrate resulted in larger thermal strain in solder joint. With larger chip size and smaller bump size, the thermal strain in the solder joint is increased with distance from chip center. In addition, the use of higher reflow temperature for Pb free solder process has further aggravated the overall package stress. The combined effect of large die size, finer bump pitch, Pb free solder packaging on advanced Cu/low κ chip is expected to be more challenging, hence it is imperative to study the chip-package interaction more closely for improving the overall robustness of Cu/low κ package. The chip locations with direct connection and interaction with packaging materials such as the region underneath solder bump are the key interest for investigation. This paper presents the study on the effect of low κ stacked layer, chip pad design structures, and shift pad design of a large die size Cu/low κ (BD) chip for improving assembly and reliability performance on organic buildup substrate FCBGA. Bump shear characterization has been performed to compare mechanical robustness of low κ stacked and pad structures. Bump shear modeling analysis and reliability testing were also performed to identify the best solution and finally implemented on a reliability test vehicle for package level reliability test verification. In addition, a potential chip crack problem encountered in FCBGA with large die assembly has been examined and a simple failure criterion based on maximum bending stress and critical chip strength obtained from 3-point bending test is proposed in the paper. I) Study on effect of Low K stack Test sample and characterization Traditionally Si3N4 and SiO2 have been employed for protecting the metallization and circuitry in the chip. For Cu low κ chip, some extra layers of passivation may be included for better protection and to act as stress buffer for the Cu/low κ layer underneath the bumps. For this purpose, three different low κ stack structures have been fabricated as shown in Figure 1. The 15 layer structure correspond to the standard 3 metal layer Cu/low κ test device available in our laboratory, hence it is adopted as control. It consisted of 2 stacks of Si3N4/USG layer due to process requirement for passivation opening on the metal pad. The other structures represent one stack Si3N4/USG short (e.g. 13 layers) and one stack extra (e.g. 18 layers) compared to the standard 15 layers. This means the 18 layers structure has additional 2 layers of 3000Å of USG with one Si3N4 on top of the standard 15 layers structure. Presumably these additional passivation layers provide further protection to the low κ stack below it. On the other hand, the 13 layers structure has excluded a 5000 Å USG layer in its passivation hence reducing its cushion effect. A fourth sample with additional polyimide layer on the standard was included represent that of a redistribution layer (RDL). The standard blanket wafer fabrication procedures have been adopted except that there is absent of Cu metallization layer within the low κ stacked layers. For electrical continuity checking purpose, a simple daisy chain was formed using the top Cu electroplated metal layer for a die size of 17.5mm x 17.5 mm, with 150 um bump pitch of 10 peripherals rows. Spin coated 978-1-4244-2231-9/08/$25.00 ©2008 IEEE 38 2008 Electronic Components and Technology Conference polymer dielectric is formed on the top metal layer followed by electroplated TiW/Cu UBM and Sn2.5Ag solder [8]. The schematic of bumped chip samples are shown in Figure 2. a) 13 layers b) 15 layers c) 18 layers Figure 1: Blanket low κ stacked structures Figure 2: Bump structures Initial dicing experiment was performed using straight dicing but peeling was encountered in all the samples. Dicing optimization was performed using 2-step process with a 45 degree bevel dicing followed by straight dicing. Optical and SEM inspection on dicing edges confirmed 2-steps dicing without any sign of delamination, see Figure 3. To further confirm the robustness of the 2-step dicing, the dicing water flow rate was increased from the normal 0.5 litre/minute to 1.0 litre/minute while the spindle speed is keeping at 30krpm and table speed at 30mm/sec for process throughput. Presumably the higher water jet impingement to the dicing edge is worst when water flow rate is increased however the dicing edge quality remained good for the all samples. 13 layer 15 layer 15+ PI layer 18 layer Figure 3: Dicing quality check of low κ stacked wafer After that, the diced chips were subjected bump shear characterization after multiple reflow exposure at peak temperature of 260°C and thermal aging of 150°C for 1000 hours. Shear height was 15um and shear speed 0.05 mm/sec. The results show only bulk solder shear failure for all the 4 types of low κ structures. Typical failure modes of the samples are shown in Figure 4. In addition, CSAM (C-Mode Scanning Acoustic Microscopy) was performed on the bump sheared chips to verify if there was any delamination below bump area. Typical of the CSAM images are shown in Figure 5 where no delamination was detected (e.g. in the circled area). These initial chip level characterization results do not show any significant differences among the 4 types of low κ structures. Further analysis need to be performed for comparison of them. 13 layer 15 layer 15+PI layer 18 layer a) after 10x multiple reflow b) after 150C for 1000 hours Figure 4: Bump shear failure mode Figure 5: CSAM images on bump sheared sample Bump shear modeling The bump shear test was modeled with FE (Finite Element) method to reveal stresses distribution and the interfacial stresses in the low κ stacked layer underneath the bump. 2D plain strain FE model as shown in Figure 6 with shear ram modeled as rigid part without deformation. UBM layer was considered as bilinear plastic, solder as elasticplastic and the rest of material including the low κ stacked layers as elastic material. [9] Figure 7 shows the peel stress distribution in the structure at 5um shear displacement into the solder. The region directly under the shear ram shows strongest effect. Maximum peel stress is found to occur at top interface of Blok/BD in the low κ structure. In addition to the shear height of 15um, the thickness of UBM has further contributed to the shear distance from shear tip to the low κ stack layer below it. The resultant 3KÅ SiN